Stadium size displays have been used in the past to present video information to audiences. However these displays are in general low pixel density devices meant for viewing at large distances. As such, these displays need only be low resolution devices.
On the other hand, there exists a need for large megapixel high resolution displays, viewed within a few feet for applications as diverse as CAD/CAM design, motion picture editing, map display, blueprints, white boards and detailed control panels. These appreciations require more than the multiple TV monitor approach used for advertising or auditorium use because of the detail that must be represented in a single field of view. For instance, a 6000.times.2000 pixel display of 12 megapixels is required to permit detailed editing of motion pictures in a single field of view. In order to obtain enough definition, one must dramatically increase the pixel density and be able to quickly address this massive number of pixels in real time.
While megapixel displays are presently feasible, one of the major problems in the display of images across such large high pixel density displays has been the difficulty in driving these displays in real time. This is due to the large amount of data which must be transmitted to drive all of the display. For the above-mentioned 2,000.times.6000 pixel display of 2 ft..times.6 ft., with 24 bits per pixel, 288 Mbits are required per image. For full motion video, transmitted pixel by pixel at 30 frames per second, 8.64 Gbits per second communication must be provided between source and display. However, the fastest communication I/O bus can transmit only 0.2 Gbits per second.
Because of bus limitations, when such a large wall-size display is to be driven by a central processing unit (CPU) which serves as a video source generator for the display, it takes tens of minutes to provide or "paint" the image across the display. This is because all of the individual pixels are addressed through a speed-limited network or communications channel between the source of video images and the passive modules used to drive different segments of the display.
Note that passive modules include only a display element and driver. Such passive modules are described in U.S. Pat. No. 5,067,021. Other low pixel density modular display systems are described in U.S. Pat. Nos. 5,129,028; 5,109,348; 5,107,534; 5,057,739; 5,011,277; 4,978,952; 4,935,880; 4,901,155; 4,874,227; 4,866,530; 4,833,542; 4,772,942; 4,769,680; 4,760,388; 4,720,803; 4,410,887; and, 4,384,279.
Driving all of the above modular displays is painfully slow due to the limited bandwidth of the serial buses utilized. In general, these passive modules are to be driven from a central processor or video source generator which routes video material or information to the modules responsible for various segments of the display over a so-called VME bus. Since none of the modules have associated processors and are thus passive in the process, the result is that there is a data bottleneck at the bus. With all of the computing power carried at the central processor, there is a massive amount of raw data which must be transmitted over the conventional bandwidth-limited VME bus. Noting that the numbers of multiplications per second to "paint" an image across such a large high pixel density display is in the billions for full motion video, maintaining and updating the display through current bus structures and passive modules is unacceptably slow. For instance, in one application, it takes over 24 minutes to provide an image over the above 6 ft..times.2 ft. modular display due to the bandwidth limitations of the communication channel.
By way of further background, in terms of how images are normally generated, image-generating software programs running on a CPU typically convert structured data representing the visual information being displayed into pixels, with each pixel being the digital representation of a single, small spot of light on the display.
The structured data includes the digital representations of text; lines, arcs, polygons, and other graphical objects; and digital encoding of images captured by cameras, called sampled images.
Pixels generated at the CPU or other video source generator are typically written to a frame buffer, a designated portion of computer memory. A device controller is interposed between the frame buffer and the display device which reads pixels from the frame buffer and converts them to a form suitable for transmission to a display device such as LCD display or a projector. The device controller repeatedly reads all of the pixels of the visual information being displayed, thereby "refreshing" the display device in order to present a persistently visible image. In normal computer display systems, the device control reads all pixels approximately 60 to 72 times per second.
The frame buffer is usually either a designated region of ordinary computer memory, a separate bank of computer memory, or a special kind of computer memory device such as Video-RAM.
When the generator of visual information wishes to change the image or information seen on the display, it generates new structured data. Software programs in the CPU then convert this new data to pixels and write them to the frame buffer. Because the device controller for the display is repeatedly reading the frame buffer to refresh the display, the new visual information is guaranteed to be displayed within one refresh cycle.
The amount of computation required to convert the new structured data to pixels is proportional to both the number of pixels in the area to be updated and the complexity of the visual information being displayed. The complexity of the visual information is based on the number of colors, and the degree of sophistication of the graphic objects.
For straight text and a 12 megapixel display, considering a computer with a CPU capable of 10 million instructions per second, were it not for bandwidth limitations of the communications channel, with a display of twelve million pixels, a frame buffer capable of holding pixels of eight bits each can paint the entire area of the display with text in approximately 2-4 seconds.
With respect to colored images, this requires approximately 4 multiplication operations per pixel per color component of the resulting image. Thus, painting a sampled image with three color components (red, green and blue) into an area of twelve million pixels requires 144 million multiply operations. This takes approximately 14 seconds to cover a 12 megapixel screen with the sampled image. The above assumes a 10 million instruction per second machine.
Note that for full motion video, one must paint an image every 1/30th of a second. Thus, the above system which can paint only one frame every 14 seconds is clearly insufficient. The limiting factor is not ultimately computer power but rather bus bandwidth. It is possible to provide faster computers which run at many more million instructions per second to reduce painting to the order of a second or less. However, present bus structure prevents taking advantage of such computational power. For instance, considering that video information consists of frames at rates of approximately 30 frames per second, with each frame being a sampled image, to display full motion video information in an area of 12 megapixels requires 30 times the number of operations of one sampled image, or 4.32 billion operations per second. This translates into data rates over a bus of 1.08 Gbytes/sec. Assuming such computational power, this is far beyond the capability of any present bus structure, i.e., 0.1-0.2 Gbytes/sec.
In an attempt to overcome the lengthy amounts of time required to update a display, accelerators have been provided, which off-loads from the CPU some of the computation required to paint graphics and sampled images. However, accelerators do not solve the problem of transmitting massive amounts of data to a high pixel density display. Rather, accelerators divide up the computational tasks prior to communicating the results to passive display modules over a conventional VME bus, which still remains the bottleneck.
Moreover, accelerators are specialized devices with their own graphics drawing packages to be able to paint lines on a single monitor. There is no intermodule communication to be able to distribute processing tasks between monitors or modules. Nor is there any attempt to accommodate increased numbers of pixels for better resolution. Note, as far as networks are concerned, it is possible to separate the generator of visual information from the computer system on which it is displayed. The generator transmits structured information, e.g. text, graphic information (lines, arcs, polygons, etc.), sampled images, and compressed images, over a computer network to another computer workstation. At the second computer, called the server, the CPU converts the structured data to pixels.
However, this again does not solve the problem of driving a large area display from the server, because the massive amount of pixel data must nonetheless be transmitted from the server to the display over a bandwidth limited bus.